The present invention relates generally to integrated circuits and, more particularly, to a method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop.
In many applications using integrated circuits, an external clock signal has to be interfaced with an application in the integrated circuit. In order to ensure that the internal clock signal used by the integrated circuit application is in phase with the external clock signal, delay-locked loops or phase-locked loops are often implemented as an interface between the two signals. For example, by feeding back the internal clock signal to a phase detector in a phase-locked loop and by providing the external clock signal to the phase detector, the phase-locked loop can acquire phase lock by forcing the difference between the two clock signals to be approximately zero.
However, for certain integrated circuit applications, the internal clock signal desired may be one that is different from the external clock signal. For example, the desired internal clock signal may be one that is delayed with respect to the external clock signal, or the desired internal clock signal may be one that leads the external clock signal. In these situations, the external clock signal and the internal clock signal may not be interfaced using a conventional phase-locked loop.
In accordance with the present invention, a method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop are provided that substantially eliminate or reduce disadvantages and problems associated with conventional systems and methods. In particular, a skewed output clock signal that leads or follows an external clock signal is generated by the phase-locked loop, which includes a delay element that delays either the skewed output clock signal or the external clock signal before providing the delayed signal to a phase detector in the phase-locked loop. The length of the delay is based on a skew select signal that is programmable by a user such that the skew may be adjusted based on the delay desired for a particular application.
According to one embodiment of the present invention, a method for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes receiving a feedback signal. A skew select signal is received. The feedback signal is delayed based on the skew select signal to generate a delay output signal. The delay output signal is provided to a phase detector. An external clock signal and the delay output signal are received at the phase detector. A phase detector signal is generated based on the external clock signal and the delay output signal. A skewed clock signal and the feedback signal are generated based on the phase detector signal.
According to another embodiment of the present invention, a system for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes a delay element, a phase detector, a voltage-controlled oscillator and a distribution network. The delay element is operable to receive a feedback signal and a skew select signal and to delay the feedback signal based on the skew select signal to generate a delay output signal. The phase detector is coupled to the delay element. The phase detector is operable to receive an external clock signal and the delay output signal and to generate a phase detector signal based on the external clock signal and the delay output signal. The voltage-controlled oscillator is coupled to the phase detector. The voltage-controlled oscillator is operable to receive the phase detector signal and to generate an output clock signal based on the phase detector signal. The distribution network is coupled to the voltage-controlled oscillator. The distribution network is operable to receive the output clock signal and to generate a skewed clock signal and the feedback signal based on the output clock signal.
According to another embodiment of the present invention, a phase-locked loop is provided that includes a delay element, a phase detector and a voltage-controlled oscillator. The delay element is operable to receive a feedback signal and a skew select signal and to delay the feedback signal based on the skew select signal to generate a delay output signal. The phase detector is coupled to the delay element. The phase detector is operable to receive an external clock signal and the delay output signal and to generate a phase detector signal based on the external clock signal and the delay output signal. The voltage-controlled oscillator is coupled to the phase detector. The voltage-controlled oscillator is operable to receive the phase detector signal and to generate an output clock signal based on the phase detector signal.
According to yet another embodiment of the present invention, a method for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes receiving an external clock signal. A skew select signal is received. The external clock signal is delayed based on the skew select signal to generate a delay output signal. The delay output signal is provided to a phase detector. A feedback signal and the delay output signal are received at the phase detector. A phase detector signal is generated based on the feedback signal and the delay output signal. A skewed clock signal and the feedback signal are generated based on the phase detector signal.
Technical advantages of one or more embodiments of the present invention include providing an improved method for clock deskewing. In a particular embodiment, a phase-locked loop includes a delay element that delays either a skewed output clock signal or an external clock signal before providing the delayed signal to a phase detector in the phase-locked loop. The length of the delay is based on a skew select signal. The phase-locked loop acquires phase lock such that the phase difference between either the external clock signal and the delayed output clock signal or the delayed external clock signal and the output clock signal is approximately zero. As a result, a skewed output clock signal may be generated for internal use on an integrated circuit based on an external clock signal, with the skewed output clock signal leading or following the external clock signal by an amount equal to the propagation delay through the delay element. Accordingly, the amount of skew is programmable through the use of the skew select signal such that a user may adjust the skew based on the delay desired for a particular application.
Technical advantages of one or more embodiments of the present invention also include providing a phase-locked loop operable to generate a skewed output clock signal using a continuously calibrated delay element with minimal analog bias support circuitry, relatively small area and power requirements, and reduced sensitivity to process variation.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, well as future uses of such defined words and phrases.